1. Field of the Invention
The present invention relates to package substrates and package structures, and more particularly, to a package substrate having a plurality of dielectric layer and a plurality of circuit layers alternately stacked on one another and a package structure having the package substrate.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
FIG. 1 is a schematic cross-sectional view of a conventional flip-chip package substrate. Referring to FIG. 1, the package substrate 1 has a plurality of circuit layers 11 therein. The circuit layers 11 have a same thickness, e.g., 19 um.
However, during a temperature cycle test of a flip-chip packaging process, warpage easily occurs to the package substrate due to a big CTE (Coefficient of Thermal Expansion) mismatch or asymmetrical heating between the chip and the package substrate. Consequently, it becomes difficult to form good joints between conductive bumps around an outer periphery of the chip and contacts of the package substrate, thereby reducing the product yield.
To overcome the above-described drawback of warpage of the package substrate, the thickness of the circuit layers can be increased. However, such an increase in the thickness of the circuit layers results in an increase of the overall thickness of the package substrate as well as the final package structure, thereby hindering miniaturization of electronic products.
Therefore, how to overcome the above-described drawbacks has become critical.